; JED2EQN -- JEDEC file to Boolean Equations disassembler (Version V063)
; Copyright (c) National Semiconductor Corporation 1990-1993
; Disassembled from ipi-u04.jed. Date: 2023-02-11
;
; Edited but not tested!
;
; Seems to be the STEbus address decoder
;
;

chip ipi-u04 PAL16R4

CLK		= 1	; CPU clock oscillator, e.g. 13 MHz
/selected	= 2 	; the /(P=Q) output from the 74LS688 address comparator

a3	= 3		; via U7 
a2	= 4 		; via U7 
a1	= 5		; via U7 
; a0	= 6		; connected but not used 
cm2	= 7 		; via U7 
cm1	= 8 		; via U7. Like memory/!io
cm0	= 9 		; via U7. Like R/!W 
GND	= 10 
/OE	= 11 		; grounded
;
; FIFO pin functions depend on the bus interface selected.
; M1 and M0 set the interface for Port 1 on the left, 
; B1 and B0 set the interface for Port 2 on the right.
; M1 = 1, M0 = 0, selects "non-Z-bus" for the Z180 side.
; B1 and B0 are bits in a register, so one has to inspect the firmware.
; For now I will make an educated guess
; that the STEbus side is also "non-Z-bus".
;
;
/fifo_wr	= 12	; pin 36
/fifo_rd	= 13 	; pin 37
/fifo_cs	= 14 	; pin 35
;
;
;
/state_bit_1	= 15 
/state_bit_0	= 16 
;
/ste_data_acknowledge	= 17	; to U17 pin 13

; ste_data_acknowledge track is from pin 12 of U17, 
;
; Data strobe seems to be missing!
;
i18	= 18 			; possibly address strobe?
ste_data_strobe	= 19		; to pin 2 of RP 2, a 1k pullup. 
;
; Address strobe is pin 2 of U7, emerging at pin 18 where it goes to the LS688 comparator.
;
;
; ste_data_strobe and ste_data_acknowledge seem to be shorted on PCB.
;

VCC	= 20 

;
; intermediate terms:
;
offset_0	=	/a3 * /a2 * /a1
offset_2	=	/a3 * /a2 *  a1
offset_4	=	/a3 *  a2 * /a1
offset_6	=	/a3 *  a2 *  a1

ste_io		= cm2 * /cm1
ste_io_rd	= ste_io *  cm0
ste_io_wr	= ste_io * /cm0

state_0		= /state_bit_1 * /state_bit_0
state_1		= /state_bit_1 *  state_bit_0
state_2		=  state_bit_1 * /state_bit_0
state_3		=  state_bit_1 * /state_bit_0


;
equations

ste_data_acknowledge	:= state_1 * /fifo_cs
		+  state_3 *  fifo_cs *  ste_data_acknowledge * /ste_data_strobe
		+  state_2 *  fifo_cs * /ste_data_acknowledge * i18
		+  state_1 * /fifo_cs * /ste_data_strobe * /ste_data_acknowledge


state_bit_0	:=  state_1 * /fifo_cs
		+ state_1 * /fifo_cs * /ste_data_strobe * /ste_data_acknowledge
		+ state_0 * ste_data_acknowledge * /fifo_cs * ste_io_wr * selected * offset_2 * /ste_data_strobe


state_bit_1	:= /state_bit_0 * state_bit_1 * fifo_cs * /ste_data_strobe
		+  state_2  * /ste_data_acknowledge* fifo_cs
		+  state_0 * /ste_data_acknowledge * /fifo_cs * selected * /ste_data_strobe * offset_0 * ste_io

/ste_data_acknowledge.oe	= OE
/state_bit_0.oe	= OE
/state_bit_1.oe	= OE

fifo_cs		:= /ste_data_strobe * /state_bit_0 * state_bit_1 * fifo_cs
		+  state_2  * /ste_data_acknowledge * fifo_cs
		+ selected * /ste_data_strobe * offset_0 *  state_0 * /ste_data_acknowledge * /fifo_cs * ste_io

/fifo_cs.oe	= OE

fifo_rd		= selected * offset_0 * ste_io_rd * /ste_data_strobe
fifo_wr		= selected * offset_0 * ste_io_wr * /ste_data_strobe

/fifo_rd.oe	= vcc
/fifo_wr.oe	= vcc